The subject matter of this application is directed to analog-to-digital (ADC) converters, and more particularly to shuffling inputs of a flash ADC.
Flash ADCs include comparators to compare an analog input signal to a plurality of reference voltages provided by a voltage ladder. The voltage ladder includes resistors connected in series to provide a plurality of reference voltages. Each comparator provides an output based on the comparison of the input signal to the one of the coupled reference voltages from the voltage ladder.
Outputs of the comparators are provided to a digital encoder generating a digital signal representing the analog input signal. In some application, the outputs of the flash ADC are provided to digital-to-analog (DAC) converters for further processing. Due to the mismatch in unit elements of the DACs, dynamic element matching schemes are applied to the outputs of the flash ADC to perform shuffling in the digital domain before the DAC receives the digital signals. However, the digital logic associated with such schemes introduces a delay, as time is needed to propagate the DAC bits through the digital shuffling block. For high-speed applications such delays are unacceptable.
To take account of the mismatch in the DAC unit elements, some methods perform the shuffling on the ADC side. However, these methods use complex switching techniques and/or significant routing circuitry on the inputs to the comparators.
Accordingly, there is a need in the art for shuffling of a flash ADC that is simple and applicable with high-speed operations.